1. Field of the Invention
The present general inventive concept relates to a wiring substrate, a tape package having the same, and a display device having the same. More particularly, the present general inventive concept relates to a wiring substrate for mounting a semiconductor chip, a tape package having the same, and a display device having the same.
2. Description of the Related Art
Generally, semiconductor devices may be manufactured by a fabrication process for forming electrical circuits including electrical elements on a semiconductor substrate, e.g., a silicon wafer, an electrical die sorting (EDS) process for inspecting electrical properties of semiconductor chips formed by the fabrication process, and a packaging process for sealing the semiconductor chips with resin such as epoxy, and sorting the semiconductor chips.
Semiconductor chips may be electrically connected to a substrate by various methods. For example, methods of electrically connecting a semiconductor chip to a substrate may include a wire bonding process, a solder bonding process, and a tape automated bonding (TAB) process. A semiconductor device, e.g., a semiconductor chip electrically connected to a substrate, and/or a semiconductor chip package may be sealed or encapsulated with a resin during the packaging process. The resin may protect the semiconductor device and/or semiconductor chip from the environment. The semiconductor package including the semiconductor chip mounted on a substrate may also dissipate heat from the semiconductor chip to the outside through various cooling mechanisms.
A tape package is a semiconductor package using a tape substrate. The tape package may be classified as either a tape carrier package (TCP) or a chip-on-film (COF) package. Tape packages, which may be used as a driver integrated circuit (IC) component for flat-panel displays (FPDs), owe their growth to the development of the manufacturing industry for FPDs, e.g., liquid crystal displays (LCDs).
The TCP may have a structure where the semiconductor chip is bonded to an inner lead, which is exposed through a window of the tape substrate, by an inner lead bonding (ILB) process. The COF package may have a structure where the semiconductor chip is mounted on the tape substrate having no windows, and mounted by a flip-chip bonding process.
Generally, input/output (I/O) wiring patterns formed on the tape substrate may be used as external connection terminals in the TAB process. The I/O wiring patterns may be directly adhered to a printed circuit board (PCB) or a display panel to manufacture the tape package.
For example, the semiconductor chip of the COF package may be mounted on a base film. In this case, bumps are formed in a peripheral region of the semiconductor chip and the semiconductor chip is mounted on the base film via the bumps by a flip-chip bonding process.
I/O wirings are formed on the base film. The I/O wirings include a connection end portion that is adhered to the bump of the semiconductor chip. A solder resist may be coated on the base film outside a chip-mounting region where the semiconductor chip is mounted thereon to protect the I/O wirings from the outside. On the other hand, the semiconductor chip may be mounted on the chip-mounting region that is exposed by the solder resist.
The wiring pattern of the tape package is required to have a finer pitch as FPDs are becoming miniaturized, slimmer and lightweight. Accordingly, pitches between the bumps of the semiconductor chip and between the I/O wirings are being reduced.
However, in conventional COF packages, alignment errors between the bumps and the I/O wires, which are adhered to each other, may occur in the chip-mounting region due to the fine pitches. Further, shorts between adjacent I/O wirings or between the bumps and the I/O wires may occur.